l'interface de communication firewire ieee 1394

Initial performance measures show that the FPI consumes less that 0.15 W of power. Since the FPI needs to support bi-directional communication, we also present a generic HDL model for bi-directional data sharing, which can be used in similar bi-directional applications. We used Verilog Hardware Description Language (HDL) to synthesize the FPI design. The goal of this research is to map isochronous Firewire packets into Ethernet frames by utilizing the SPEED Ethernet channel assignment capability. The FPI also manages the SPEED hardware interrupt signals in a bi-directional communication scheme.

A crucial function of the FPI design is to convert the IEEE 1394 isochronous traffic to the Ethernet frame format via two independent asynchronous write and read buffers. In this article, we integrate the chip with a Firewire peripheral interface (FPI). The novel chip utilizes the concept of Ethernet channels, where Ethernet frames are addressed in a multicast addressing scheme.

This simplification is not only required to fit in a hardware solution, but also it improves network performance. The main function of this chip (named SPEED) is to bypass the operating system processing of network protocol stack at the host computer by off-loading its networking functions to hardware. In a related research, the authors designed a novel high-performance custom network processor chip using field programmable gate arrays (FPGAs).

Bandwidth demands on ubiquitous Ethernet have grown immensely, driven by the rapid expansion of real-time applications like audio/video streaming.

L'interface de communication firewire ieee 1394